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[VHDL-FPGA-Verilog] cpu16

Description: 一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
Platform: | Size: 3072 | Author: 王林 | Hits:

[VHDL-FPGA-Verilog] VHDL例程

Description: 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看-lot of routines, to learn VHDL programming of great help, I can not see
Platform: | Size: 168960 | Author: 周 | Hits:

[VHDL-FPGA-Verilog] 数字系统设计教程4_9

Description: vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
Platform: | Size: 244736 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] 数字系统设计相关

Description: 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
Platform: | Size: 45056 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] booth_mul

Description: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Platform: | Size: 19456 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] RISC

Description: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Platform: | Size: 128000 | Author: 12 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_creative

Description: 一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
Platform: | Size: 1866752 | Author: 梁文锋 | Hits:

[VHDL-FPGA-Verilog] risc-8

Description: 一个VHDL实现的RISC8位单片机-the RISC8 bit microcontrollers
Platform: | Size: 76800 | Author: 刘恩树 | Hits:

[VHDL-FPGA-Verilog] addch1

Description: 用vhdl语言设计CPU中的一部分：加法器的设计，包括多种加法器的设计方法！内容为英文-design using VHDL language part of the CPU : Adder design, Adder including multiple design! As for the English
Platform: | Size: 393216 | Author: qindao | Hits:

[VHDL-FPGA-Verilog] mul6

Description: 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Platform: | Size: 462848 | Author: qindao | Hits:

[OS Develop] ARM_00_OS

Description: 看看ARM菜鸟在ARM7上写的操作系统——ARM圈圈操作系统 最近在ADuC7027上写了一个ARM_00_OS，头都写晕了，发上来给大家一起来看看。 任务按优先级调度，如果处于就绪态且优先级最高的任务有两个或更多，则按时间片轮循调度。 支持任务创建、任务删除、内存分配、简单的消息、简单的设备管理、CPU及内存等使用统计等功能。 任务可处于ARM模式或THUMB模式，在创建任务时，要指定任务所处于的模式。 从这里下载整个文件包：http://blog.21ic.com/more.asp?name=computer00&id=16341 -look at birdie in ARM ARM7 written in the operating system-- the operating system ARM circle recently in ADu C7027 write a ARM_00_OS, write head dizzy, deputy undersecretary for everyone to see. Tasks according to priority scheduling, in place if the state but the highest priority tasks of two or more, according to the time-Round Robin scheduling. Support mission to create, delete tasks, memory allocation, the simple information, a simple device management, CPU and memory usage statistics capabilities. At tasks THUMB ARM model or models in the creation mandate, the mandate should be designated at a model. From here to download the whole package : http :// blog.21ic.com/more.asp name = computer00
Platform: | Size: 360448 | Author: Computer00 | Hits:

[Post-TeleCom sofeware systems] Behaviouralmodelofasimple8-bitCPU

Description: 个人认为几个比较实用的VHDL源码之二——Behavioural model of a simple 8-bit CPU-think of a few more practical VHDL source bis-- Behavioral mode l of a simple 8-bit CPU
Platform: | Size: 1024 | Author: xingqiba | Hits:

[Books] MCUDesign

Description: 《Digital Logic And Microprocessor Design With VHDL》，CPU设计经典参考书-"Digital Logic And Microprocessor Design With VHDL, "CPU design classic reference books
Platform: | Size: 4815872 | Author: hanberg | Hits:

[VHDL-FPGA-Verilog] cpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[VHDL-FPGA-Verilog] vhdl_8cpu

Description: VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code
Platform: | Size: 52224 | Author: 紫蓝 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[source in ebook] CPU_use

Description: 使用VHDL语言编写的简单8位流水线CPU 它有六级流水功能，通过仿真 可以下载到实验箱，也有波形仿真-use VHDL to prepare a simple eight pipelined CPU it has six functional water, Simulation experiments can be downloaded to the box, a waveform simulation
Platform: | Size: 1530880 | Author: 邮件 | Hits:

[VHDL-FPGA-Verilog] vhdlfinishcpu

Description: 用vhdl实现简单cpu的功能,能够很好的帮助特别是初学者学习vhdl的功能!-with vhdl cpu to achieve simple function can be very helpful, especially beginners learning vhdl function!
Platform: | Size: 53248 | Author: 敖鱼 | Hits:

[Other] CPU8

Description: 本源码实现了8为cpu，开发语言为vhdl，里面有详细的文档和vhdl工程源码-the source to achieve the 8 cpu, development language for vhdl. There are detailed documentation and source code works vhdl
Platform: | Size: 732160 | Author: digg | Hits:

[MPI] sdgshjd

Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar]- 4 division of vhdl source [vh dl example. rar]- highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Platform: | Size: 1024 | Author: 张瑞 | Hits:
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